Congestion is at the heart of the design closure challenge today. With smaller cell dimensions, increased chip-size and an inclination of design houses to reduce metal layers available for routing (to save costs), designs are getting more congested. The normal approach to solve congestion has been to increase the die size which increases design cost. Hence it is desirable to have a comprehensive implementation flow in place which tackles congestion from RTL to detailed routing.

Congestion is caused primarily due to two reasons:

* Connectivity – this is manifested in the RTL itself. E.g. a cross-bar switch design tends to be more congested than a basic processor design.
* Floorplan – essentially how your hard macros are placed. Since the macro placement is sometimes a direct outcome of higher-level chip planning, one has no option but to live with sub-optimal macro placement.

Traditionally congestion has not been something front-end designers have worried about and nor have the commercially available front-end synthesis tools addressed the problem.

There are many reasons for this:

* Congestion is really a manifestation of placement and synthesis tools have stayed away from placement
* A floorplan is not available at synthesis stage or tools don’t support reading one
* Synthesis tools have been weak in supporting multi-objective optimizations
* Techniques to estimate congestion in front-end (e.g. pin count, net-count etc.) have been generally ineffective

But, the fact of the matter is that synthesis tools create the circuit topology and connectivity and hence have a significant impact on how congested a design will be in the back-end.

Why should the front-end engineer care?

The front-end designer is the only link between the RTL developer and the implementation team. As described above congestion in the design core is a direct result of the RTL architecture. Although there are various techniques designed to alleviate congestion in the implementation tools, it often requires a RTL change. Back-end tools do not provide links to the RTL and it makes it extremely difficult to analyze and identify the root cause. Hence, it is desirable that the front-end designer be able to identify congestion hot-spots and give feedback to the RTL designer early in the development cycle. In addition, the front-end engineer really doesn’t want to spend time doing DFT, verification etc. on a RTL code which would be changed frequently. Early identification of congestion saves a lot of effort and design cycles.

RTL Compiler Physical has a comprehensive set of technologies to estimate, analyze and optimize congestion at various stages in the design flow from RTL to placed gates. It looks at congestion both in global terms during RTL synthesis and also at the local level post placement.

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